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CLA60000 Series
Channel less CMOS Gate Arrays
This new family of gate arrays uses many innovative techniques to achieve 110K gates per chip with system clock speeds of up to 70MHz. The combination of high speed, high gate complexity and low power operation places Zarlink Semiconductor at the forefront of ASIC capability.
General Description
The CLA60000 gate array family is Zarlink Semiconductor's fifth-generation CMOS gate array product. These arrays allow even higher integration densities at enhanced system clock rates as need for many of today's system applications. The largest array in the family at 110K gates offers a tenfold increase in raw gate availability then channelled gate arrays. In addition, many new designs features have been incorporated such as analog functionality, slew rate output control, and intermediate I/O buffering for optimum data transfer through peripheral cells. Also, the low-power characteristics of Zarlink Semiconductor CMOS processing have been incorporated in these arrays, easing the thermal management problems associated with complex designs of 20,000 gates and above.
Features
* * * * * * * * Channel less arrays to 110,000 gates 1.4 micron dual layer metal silicon CMOS process Typical Gate Delays of 700ps (NAND2) Comprehensive cell library including microcells, macrocells, and paracells Power distribution optimized for maximum noise immunity Slew controlled outputs with up to 24mA drivers Fully supported by design software (PDS2) and popular workstations Very high latch up immunity
Figure 1 - CLA60000 Chip Microplot All CLA60000 arrays have the same construction. A core of uncommitted transistors is arranged for optimum connection as logic functions and surrounded by uncommitted peripheral (I/O) circuitry. The channel less array architecture is an important feature - the absence of discrete wiring channels increases flexibility, reduces track capacitance whilst significantly increasing transistor sizes for improved logic performance. The construction of the basic building blocks have been planned to support basic logic functions, macro functions, and core memory functions (RAM and ROM) with high routability. Logic programmability is given by dual level metal, with interconnecting vias, plus a forth level of programmability (contacts). The overall architecture of these gate arrays has been designed to exploit many new and emerging developments in CAD tools. Increasing demands are now being made for design tools which are faster, easier to use, and more accurate. The Zarlink Semiconductor Design System (PDS2) allows full control over all aspects of design including logic capture, simulation and layout.
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CLA60000 Series
Product Range
The CLA60000 product range is shown below. Actual gate utilization can be typically 40-70% of the uncommitted gate count depending on circuit structure. Complete rows of array elements can be used as routing channels to conform to the earlier channeled Zarlink Semiconductor arrays or, if desired, compact hierarchical logic blocks and localized routing areas can be defined like a cell based design layout. The array structure has been designed to be totally flexible in architecture with the distribution of logic blocks and routing channels being definable by the designer.
Product CLA61XXX CLA62XXX CLA63XXX CLA64XXX CLA65XXX CLA66XXX CLA67XXX CLA68XXX
Uncommitted Gate Count 2040 5488 10608 19928 35784 55616 80560 110112
Pads Including Power 40 64 88 120 160 200 240 280
I/O Buffer Arrangement
The I/O buffers are the interface to external circuitry and are therefore required to be robust and flexible. The inputs and outputs can withstand electro-static discharges, are not susceptible to latch up (an inherent CMOS problem) and provide the designer with multiple interface options.
IB1
IB2
Intermediate Buffers
Core Arrangement
A four transistor (2 NMOS and 2 PMOS) groups forms the basis of the core array. This array element is repeated in a regular fashion over the complete core area to give a `Full Field' (sea-of-gates) array. The unique design of the basic four transistor cells give the Zarlink Semiconductor arrays a major advantage over all competitors. Thesilicon layout has been configured so that the basic logic cells, flipflops and large hierarchical cells can be interconnected easily with through-cell routing channels. It also ensures that an optimum overall data flow and control signal distribution scheme is possible.
OP1 IP
OP2
Output Drivers
Bonding pad
Figure 3 - I/O Block The CLA60000 I/O buffers contain all the components for static protection, input pull-up and pull down resistors, various output drive currents and input interface signals such as CMOS and TTL. In addition, the I/O buffer contains all the components for intermediate buffering stages including Schmitt triggers, TTL threshold detectors, tristate control, signal re-timing flip-flops and slew rate control for the output drivers. Some analog interface cells can also be implemented using the available components. I/O buffer locations can also be configured as supply pads (VDD and VSS).
VDD Supply
Programmable contacts
INPUT DATA
P D N Delay Driver IB2BD IBSK1 IBSK2 IBSK3 Delay (nsec) 4.64 5.50 6.41 9.15
P OPT N
PIN 50pF
2.5V
2.5V Current Ramp (mA/nSec) 57.2 31.8 17.1 8.7
VSS Supply
Figure 2 - Array Core Cell
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Figure 4 - Slew Control
CLA60000 Series
Slew control of output drivers is a useful benefit where outputs are driving large capacitive loads such as busses. Noise transients caused by voltage coupling into peripheral power supplies can give switching problems, resulting in mis-operation. The extent of this voltage disruption is depended on the number of outputs switching, supply pad locations and the inductance of the chip bond wire/package leads. The CLA60000 family uses proprietary design techniques to reduce this phenomenon by offering output switching control (di/dt) as part of the intermediate buffers. The power distribution scheme for the CLA60000 arrays is very flexible (shown in figure 5): three separate power rings are used, one for the internal core logic, one for the large output driver cells and one for the intermediate buffer regions. Each of the separate power rings isolate any noise generated by the low-impedance output drivers from the core logic and intermediate buffers. The power rings can be connect to separate pad locations or, if required, combined at a single Input or Output pad location. In addition, it is possible to isolate sections of the peripheral supply ring for the implementation of basic analog circuits. The distribution of the supply rails across the core of the array can be automatically positioned for the interconnect of the base cells and hierarchical blocks. This allows greater design flexibility and provides additional signal routing channels. Supply interconnection is added during autolaying leaving unpopulated areas available for signal routing. Low core power dissipation is very important for high complexity circuits (see section on Thermal Management).
VSS} VDD} VSS} VDD} VDD} VSS} Analog Circuits
Supply to Logic Array Supply to Intermediate Buffers Supply to I/O Buffers
Figure 5 - Power Supply Organization
PDS2 - The Zarlink Semiconductor ASIC Design System
PDS2 is Zarlink Semiconductor's ASIC computer-aided design system. It provides a fully integrated, technology independent VLSI design system for all Zarlink Semiconductor Semi-Custom CMOS products. PDS2 allows the designer to perform all design activities from schematic entry, circuit debugging, fault grading, through to chip layout and generation of a test program for the production test of the finished ICs. Logical design of CLA60000 is realized with the same software as is used for the CLA5000 and MVA5000 families of CMOS semi-custom products. PDS2 runs on DEC VEX equipment (under VMS)* and comprise schematic entry, logic and fault simulation, extensive result examination facilities and advanced library and configuration management
tools. Layout and routing is also supported on PDS2 along with full back annotation. Hierarchical logical design is possible up to 20 levels. Supplemented by a three day training course for firsttime users, PDS2 may be used either at a Zarlink Semiconductor Design Centre or under licence at the designer's premises.
Design Support and Interfaces
Zarlink Semiconductor offers a variety of design interfaces to customers. For each interface, Zarlink Semiconductor requires a given set of information to be forwarded by the designer which is assessed at Design Reviews (1 to 4). At each stage, the design must be deemed to be acceptable by Zarlink Semiconductor Project Engineers before commencing the next stage of work. Design Reviews may be held in the designer's premises or at a Zarlink Semiconductor Design Centre.
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CLA60000 Series
Further information on PDS2 or the interfacing requirements to the Zarlink Semiconductor technologies is available from any Zarlink Semiconductor Sales Office or Design Centre. * DEC, VAX and VMS are trademarks of Digital Equipment Corporation, USA
Design Interfaces
PDS2 USED AT Zarlink DESIGN CENTRE PDS2 USED BY CUSTOMER ON OWN PREMISES Zarlink COMPLETES DESIGN TURN KEY F G WORK STATION
OPTIONS DESIGN REVIEW 1 LOGICAL DESIGN DESIGN REVIEW 2 PHYSICAL DESIGN
A
B
C
D
E
CUSTOMER
CUSTOMER
CUSTOMER
CUSTOMER
CUSTOMER
Zarlink
Zarlink
Zarlink
CUSTOMER
Zarlink
CUSTOMER
CUSTOMER (AT DESIGN CENTRE)
Zarlink
Zarlink
DESIGN REVIEW 3 PROTOTYPE MANUFACTURING PROTOTYPE EVALUATION DESIGN REVIEW 4 PRODUCTION ___________________________________ Zarlink __________________________________________ ___________________________________ ___________________________________ Zarlink __________________________________________ CUSTOMER______________________________________
Figure 6 - Access Routes to Zarlink Semi-custom
Zarlink Semiconductor operates a design audit procedure with four formal review meetings: REVIEW 1: LOGICAL DESIGN: REVIEW 2: PHYSICAL DESIGN: REVIEW 3: PROTOTYPES: Checks that the required specification can be met by the CLA60000 gate array. Conversion of the logic into hierarchical netlist. Circuit function is simulated for the eventual environmental conditions to be met by the chip, including definition of the test pattern and fault simulation. Checks that logic simulation results are acceptable to both parties, and finalizes objectives for physical design (package, pinout, etc.) Package and pinout are defined. Cells are placed and routed within the array - using Zarlink Semiconductor's interactive layout package. A final simulation is performed which takes account of real track loads. Establishes that it is appropriate to proceed with chip manufacture by comparing all PDS2 results with customer's specifications. Zarlink Semiconductor manufactures four custom masks develops a test program from the customer' simulation vectors, fabricates wafers and supplies 10 tested, packaged prototypes as standard. Additional prototypes may be supplied at extra cost. Confirms that the customer has fully examined the prototype and approves the chip design for full-scale production.
REVIEW 4:
The schematic entry and logical design work may be done by Zarlink Semiconductor, or the customer may licence the PDS2 tools with Zarlink Semiconductor providing training to enable the engineer to undertake this phase of development in house. Design rooms and equipment are also available for customer use at any Zarlink Semiconductor design centres at attractive rental rates. For the physical design phase, customers are encouraged to work with Zarlink Semiconductor layout engineers to ensure the best possible final performance. This can be completed either at a Zarlink Semiconductor design centre or at the customers premises.
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CLA60000 Series
Design Thermal Management
As gate integration capacity improves with CMOS process geometry reduction, the ability of silicon to exceed the power capabilities of accepted packaging technology is a very real problem. Semi-Custom designers now have the ability to design circuits of 50,000 gates and over, and chip power consumption is (or should be) a very important concern. With complexities approaching 100K gates, the core power at gate level becomes increasingly more dominant. It becomes essential to offer ultra low power core logic to maintain an acceptable overall chip power budget (typically 1 Watt for standard surface mount packaging). The consequences of higher power consumption are elevated chip temperatures and reductions in product reliability, otherwise relatively expensive special packaging has to be considered which is bulkier and more costly. Zarlink Semiconductor's CLA60000 arrays offer low power factors. At 5mW per gate per MHz gate power and 2mW per gate load, power is lower than most competitive arrays, with lower operating temperatures and higher inherent long term reliability.
CLA60000 Power Dissipation Calculation
CLA60000 series power dissipation for any array can be estimated by following this example (calculated for the CLA68XXX). Number of available gates Percent gates used Number of used gates Number of gates switching each clock cycle (15%) Power dissipation/gate/MHz (W) (gate fanout typically 2 loads) Total core dissipation/MHz (mW) Number of available I/O pads Percent of I/O pads used as Outputs Number of I/O pads used as Outputs Number of output buffers switching each clock cycle (20%) 110112 40% 44045 6607 Total output buffer dissipation/MHz (mW) 9 59.5 280 40 112 22 Total Power dissipation/MHz (mW) Total Power at 10MHz clock rate (W) Total Power at 25MHz clock rate (W) 27.5 87 0.87 2.18 Dissipation/output buffers/MHz/pF (W) Output loading in pF Power/output buffer/MHz (mW) 25 50 1.25
1.4 Micron CMOS Process
The 1.4 micron CMOS process Zarlink Semiconductor process variant VJ) uses the latest manufacturing techniques at Zarlink Semiconductor's Class 1, 6-inch fabrication facility in Roborough, England. The process can be described as a twin well, self aligned LOCOS isolated technology on an epitaxial substrate giving low defect density and high reliability. Effective channel length is 1.1 micron. Usable gate packaging density is 600 gates/sq.mm on two levels of metal. Devices will operate up to a maximum junction temperature of 170 Deg.C, and show excellent hardness, ESD, and stable performance.
ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Input Output Storage Voltage Voltage Voltage Temperature: Ceramic Plastic -65 -40 150 125 Deg.C Deg.C MIN -0.5 -0.5 -0.5 MAX 7.0 Vdd+0.5 Vdd+0.5 UNITS V V V RECOMMENDED OPERATING LIMITS PARAMETER Supply Voltage Input Voltage Output Voltage Current per pad Operating Temperature: Commercial Grade Industrial Grade Military Grade 0 -40 -55 70 85 125 Deg.C Deg.C Deg.C 5 MIN 3.0 Vss Vss MAX 6.0 Vdd Vdd 100 UNITS V V V mA
Operation above these absolute maximum ratings may permanently damage device characteristics and may affect reliability.
CLA60000 Series
AC Characteristics for Selected Cells
The CLA60000 technology library contains all the timing information for each cell in the design library. This information is accessible to the simulator, which calculates propagation delays for all signal paths in the circuit design. The PDS2 simulator can automatically derate timings according to the various factors such as: Supply voltage variation (from nominal 5V) Chip temperature Processing tolerance Gate fanout Input transition time Input signal polarity Interconnecting wiring For initial assessments of feasibility, worst case estimations of path delays can be done in the following manner, using the dynamic Characteristics table as a guide to the normal propagation delays at 25 Deg. C and 5V supply. * For temperatures, Zarlink Semiconductor's has derived a derating multipler (Kt) of +0.3% per Deg. C For supply voltage derating, a factor of (Kv) 25% per volt of VDD Change should be used. * * For manufacturing variation (Kp), the tolerance is 50% The maximum variation on typical delays over the Commercial grade product will be at 4.5V and 70 Deg. C ambient temperature.
tpd (max) = Kp x Kv x Kt x tpd (typ) = 1.50 x (1+(5.0 - 4.5) 0.25) x (1+(70-25) 0.003) x tpd (typ) = 1.50 x 1.13 x 1.13 x tpd (typ) = 1.91 x tpd (typ) The minimum delay, at 5.5V and 0 Deg. C will be: tpd (min) = 0.66 x (1-(5.5-5.0) x 0.25) x (1-(25-0)0.003) x tpd (typ) = 0.66 x 0.87 x 0.93 x tpd (typ) = 0.53 x tpd (typ) A similar calculation may be applied for any voltage and temperature relevant to the application. An additional "safety factor" of 20% may be applied if desired for conservative design. For worst case military grade characteristics, the performance derating multiplier is 2.57 times the commercial typical. Fanout is in gate load units
Typical Propagation Delay (nS) Symbol Fanout=2 2 Worst case Propagation Delay (nS) Commercial Fanout 4 1.65 1.05 2.27 2.01 3.24 1.66 2.76 2.44 3.10 3.02 2 1.50 0.91 1.92 1.58 2.60 1.36 2.44 2.18 2.79 2.65 Industrial Fanout 4 1.72 1.10 2.38 2.11 3.40 1.74 2.90 2.56 3.25 3.17
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INTERNAL CORE CELLS Name Cells Description
INV2 NAND2 NOR 2 DF DFRS
1 2 2 4 6
INVERTER DUAL DRIVE 2 - INPUT NAND GATE 2 - INPUT NOR GATE MASTER SLAVE MASTER SLAVE D - TYPE WITH SET AND RESET
tpLH tpHL tpLH tpHL tpLH tpHL tpLH tpHL tpLH tpHL
0.64 0.39 0.82 0.67 1.11 0.58 1.04 0.93 1.19 1.12
1.43 0.87 1.83 1.51 2.48 1.30 2.32 2.08 2.66 2.52
INTERMEDIATE BUFFER CELLS Name Cells Description Symbol
Typical Propagation Delay (nS) Fanout=2
Worst case Propagation Delay (nS) Commercial Fanout 2 4 2.05 1.40 2.76 2.44 2.88 1.83 2 1.77 1.19 2.44 2.18 2.60 1.69 Industrial Fanout 4 2.15 1.47 2.90 2.56 3.02 1.92
IBGATE IBDF IBCMOS1
-
LARGE 2 INPUT NAND GATE + 2 INPUT NOR MASTER SLAVE D-TYPE FLIP FLOP CMOS INPUT BUFFER WITH 2 INPUT NAND GATE
tpLH tpHL tpLH tpHL tpLH tpHL
0.76 0.50 1.04 0.93 1.11 0.72
1.69 1.13 2.32 2.08 2.48 1.61
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CLA60000 Series
INTERMEDIATE BUFFER CELLS Name Cells Description Symbol Typical Propagation Delay (nS) Fanout=2 2 OP 3 OP 6 OP 12 STANDARD OUTPUT BUFFER MEDIUM OUTPUT BUFFER LARGE OUTPUT BUFFER tpLH tpHL tpLH tpHL tpLH tpHL 2.83 2.06 0.86 0.70 0.70 0.56 2.83 2.06 1.93 1.52 1.52 1.23 Worst case Propagation Delay (nS) Commercial Fanout 4 10.03 5.66 5.53 3.12 3.12 2.03 2 2.79 2.16 2.02 1.59 1.60 1.29 Industrial Fanout 4 10.53 2.27 5.80 3.28 3.28 2.13
Note: Commercial Worst case is Industrial Worst case is Military worst case is
4.5V, 70 Deg.C operating, Worst Case processing 4.5V, 85 Deg.C operating, Worst Case processing 4.5V, 125 Deg.C operating, Worst Case processing
DC Electrical Characteristics
All characteristics at Commercial Grade voltage and temperature (Note 1)
VALUE CHARACTERISTIC SYM Min LOW LEVEL INPUT VOLTAGE TLL Inputs CMOS Inputs (IBTTL1/IBTTL2) (IBCMOS1/IBCMOS2) VIH 2.0 VDD - 1.0 VT+ VTVT+ 2.75 1.92 2.20 V VIL to VIH VIH to VIL VIL to VIH VIH to VIL IIN -5 0.2 0.1 0.05 10 5 2.5 1.2 50 +5 10 5 2.5 200 A mA mA mA mA VIN = VDD or VSS VIN = VDD or VSS VIN = VDD or VSS VIN = VDD or VSS VIN = VDD or VSS VIL 0.8 1.0 V Typ Max V UNIT CONDITIONS
HIGH LEVEL INPUT VOLTAGE TLL Inputs CMOS inputs INPUT HYSTERESIS (IBTTL1/IBTTL2) (IBCMOS1/IBCMOS2) (IBST1) Rising Falling (IBST2) Rising Falling INPUT CURRENT CMOS/TTL INPUTS Inputs with 1Kohm Resistors Inputs with 2Kohm Resistors Inputs with 4Kohm Resistors Inputs with 100Kohm Resistors Resistor values nominal - See note 2 HIGH LEVEL OUTPUT VOLTAGE All outputs Smallest drive cell Low drive cell Standard drive cell Medium drive cell Large drive cell OP1/OPOS1 OP2/OPOS2 OP3/OPOS3 OP6/OPOS6 OP12/OPOS12
VOH VDD -0.05 VDD-1.0 VDD-1.0 VDD-1.0 VDD-1.0 VDD-1.0 VOL VSS +0.05 VDD-0.5 VDD-0.5 VDD-0.5 VDD-0.5 VDD-0.5
V IOH=-1A IOH=-1mA IOH=-2mA IOH=-3mA IOH=-6mA IOH=-12mA V IOL=1A IOL=2mA
LOW LEVEL OUTPUT VOLTAGE All Outputs Smallest Drive Cell OP1/OPOD1
0.2
0.4
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CLA60000 Series
DC Electrical Characteristics (continued)
All characteristics at Commercial Grade voltage and temperature (Note 1)
VALUE CHARACTERISTIC SYM Min Low drive cell OP2/OPOS2 Standard drive cell Medium drive cell Large drive cell OP3/OPOS3 OP6/OPOS6 OP12/OPOS12 IOZ IOS IDDSB 10 Typ 0.2 0.2 0.2 0.2 Max 0.4 0.4 0.4 0.4 A mA nA IOL=4mA IOL=6mA IOL=12mA IOL=24mA UNIT CONDITIONS
TRISTATE OUTPUT LEAKAGE CURRENT OUTPUT SHORT CIRCUIT CURRENT STANDBY SUPPLY CURRENT (per gate)
Note 1: Note 2:
Note 3: Note 4: Note 5: Note 6:
Commercial grade is 0-70 deg. C, 5V 10% power supply voltage Resistor value spreads (Min-Max): LOW VALUE (Rtyp 1K) 0.5 - 2Kohm LOW VALUE (Rtyp 4K) 2K - 8Kohm LOW VALUE (Rtyp 2K) 1.0 - 4Kohm HIGH VALUE (Rtyp 100K) 25K - 250Kohm Standard driver output OP3 etc. Short circuit current for other outputs will scale. Not more than one output may be shorted at a time for a maximum duration of one second. Excluding peripheral buffers. Excludes package leadframe capacitance or bidirectional pins. Excludes package.
Packaging
Production quantities of the CLA60000 family are available in Industry-standard ceramic and plastic packages according to the codes shown below. Prototype samples are normally supplied in ceramic only. Where plastic production packages are requested, Ceramic prototypes will be supplied in the nearest equivalent and tested to the final test specification. DC DG DP AC MP LC HC GC HG GG HP GP
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DILMON CERDIP PLASDI P.G.A. SMALL OUTLINE LCC LEADED CHIP CARRIER LEADED CHIP CARRIER QUAD CERPAC QUAD CERPAC PLCC PQFP
Dual in Line, Multilayer ceramic. Brazed leads. Metal sealed lid. Through board. Dual in Line, Ceramic body. Alloy leadframe. Glass sealed. Through board. Dual in Line, Copper or Alloy leadframe. Plastic moulded. Through board. Pin Grid Array. Multilayer Ceramic. Metal sealed lid. Through board. Dual in Line `Gullwing' formed leads. Plastic moulded. Surface mount. Leadless Chip Carrier. Multilayer ceramic. Metal sealed lid. Surface mount. Quad Multilayer ceramic. Brazed `J' formed leads. Metal sealed lid. Surface mount. Quad Multilayer ceramic. Brazed `Gullwing' leads. Metal sealed lid. Surface mount. Quad ceramic body. `J' formed leads. Glass sealed. Surface mount. Quad ceramic body. `Gullwing' formed leads. Glass sealed. Surface mount. Quad Leaded plastic Chip Carrier. `J' formed leads. Plastic moulded. Surface mount. Quad plastic Flat Pack. `Gullwing' formed leads. Glass sealed. Surface mount.
CLA60000 Series
Packaging Options
The package style and pin count information is intended only as a guide. Detailed package specifications are available from Zarlink Semiconductor Design Centres on request. Available packages are being continuously updated, so if a particular package is not listed, please enquire through your Zarlink Semiconductor Sales Representative.
LEADS 16 16 16 18 18 18 20 20 20 22 22 22 24 24 24 28 28 28 40 40 40 48 48 48 16 18 20 24 28 28 28 28 28 44 44 44 44 44 48 64 68 68 68 68 80 84 84 84 84 100 100 120 132 160 172 196 68 84 100 120 132 144 180 STYLE DC DG DP DC DG DP DC DG DP DC DG DP DC DG DP DC DG DP DC DG DP DC DG DP MP MP MP MP MP HP LC HC HG HP GP LC HC HG GP GP HP LC HC HG GP HP LC HC HG GP GG GP GC GP GC GC AC AC AC AC AC AC AC CLA61 X X X X X X X X X X X X X X X X X X CLA62 CLA63 CLA64 CLA65 CLA66 CLA67 CLA68
D U A L I N L I N E
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Q U A D
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CLA60000 Series
Cell Library
A most comprehensive cell library is available in CLA60000. The implementation of a cell has involved the silicon planning, design rule checking, automatic generation of a SPICE file for performance analysis, SPICE simulation and result extraction, generation of data sheets, generation of the PDS2 simulator library code and verification of cell attributes for layout tools. The two micron CMOS array (CLA5000) cell library can be converted to equivalent cells on the CLA60000 arrays to allow system upgrades. In addition, many new functions have been made available such as RAMs, ROMs, and DSP Macros. Some macro cells are also available for implementing structured test philosophies. Also separate documentation on build-in test for gate arrays will be available in the near future.
CLA60000 Library (Library version V1R2)
Logic Array: BUF 2INV INV2 INV4 INV8 NAND2 ND3 NAND3 2NAND NAND4 NAND5 NAND6 NAND8 NOR2 NR3 NOR3 2NOR3 NOR4 NOR5 NOR 6 NOR8 A202I O2A2I 2A2O2 202A2I 2ANOR 2ONAND A2O3I O2A3I A3O2I O3A2I Non-inverting Signal Buffer Dual Inverter Inverter Dual Drive Inverter Quad Drive Inverter x 8 Drive 2-Input Nand Gate 3-Input Nand Gate 3-Input Nand Gate + Inverter 3 Dual 3-Input NAND Gate 4-Input NAND Gate 5-Input NAND Gate 6-Input NAND Gate 8-Input NAND Gate 2-Input NOR Gate 3-Input NOR Gate 3-Input NOR Gate + Inverter Dual 3-Input NOR Gate 4-Input NOR Gate 5-Input NOR Gate 6-Input NOR Gate 8-Input NOR Gate 2-Input AND to 2-Input NOR Gate + Inverter 2-Input OR to 2-input NAND Gate + Inverter Dual 2-Input AND to 2-Input NOR Gate Dual 2-INput OR to 2-Input NAND Gate 2-Input ANDs to 2-Input NOR Gate 2-Input ORs to 2-Input NAND Gate 2-Input AND to 3-Input NOR Gate 2-Input OR to 3-Input NAND Gate 3-Input AND to 2-Input NOR Gate 3-Input OR to 2-Input NAND Gate A2O4I O2A4I A4O2I O4A2I 3A2O3I 302A3I A202A2I O2A2O2I Quad 2-Input ANDs to 4-Input NOR Gate Quad 2-Input ORs to 4-Input NAND Gate Dual 4-Input ANDs to 2-INPUT NOR Gate Dual 4-Input ORs to 2-Input NAND Gate Triple 2-input ANDs to 3-Input NOR Gate Triple 2-Input ORs to 3-Input NAND Gate 2-Input AND to 2-Input OR to 2-Input NAND 2-Input OR to 2-Input AND to 2-Input NOR GND Cell VDD Cell Exclusive OR Gate + NAND Gate + Inverter Exclusive NOR Gate + NOR Gate + Inverter 2-Input Exclusive OR Gate 2-Input Exclusive NOR Gate 3-Input Exclusive OR Gate 3-Input Exclusive NOR Gate Half Adder + Inverter Sum Block Carry Block + NOR Gate Full Adder + NOR Gate 2 4 8 2 4 8 to to to to to to 1 1 1 1 1 1 Multiplexor Multiplexor Multiplexor Inverting Multiplexor Inverting Multiplexor Inverting Multiplexor
GND VDD EXOR EXNOR EXOR2 EXNOR2 EXOR 3 EXNOR3 HADD SUM CARRY FADD MUX2TO1 MUX4TO1 MUX8TO1 MUXI2TO1 MUXI4TO1 MUXI8TO1
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CLA60000 Series
CLKA 2CLKA CLKAP CLKAM CLKB DRV3 DRV6 TM 2TM BDR DL DL2 DLRS DLARS DF DFRS Basic Clock Driver Dual Basic Clock Driver Basic Clock Driver + Inverter Basic Clock Driver + Inverter Large Clock Driver + Inverter Triple Output Internal Driver Hex Output Internal Driver Buffered Transmission Gate Transmission Gate for 2 to 1 Multiplexing Bus Driver IBTRID1 IBTRID2 IBTRID3 IBGATE IB2D IBCLKB IBDF IBDFA IBCMOS1 IBCMOS2 IBTTL1 IBTTL2 Tri-State Driver with Lightly Skewed Outputs + 2 Inverters Tri-State Driver with Medium Skewed Outputs + 2 Inverters Tri-State Driver with Heavily Skewed Outputs + 2 Inverters Large 2-Input NAND Gate + Large 2Input NOR Gate Dual High Power Inverters Large Clock Driver Master-Slave D-Type Flip-Flop Master-Slave D-Type Flip-Flop CMOS Input Buffer and Large 2-Input NAND Gate CMOS Input Buffer and Data Latch TTL Input Buffer and Large 2-Input NAND Gate TTL Input Buffer and Data Latch
Data Latch Data Latch Data Latch with Set and Reset Data Latch with Set and Reset Master-Slave D-Type Flip-Flop Master-Slave D-Type Flip-Flop with Set and Reset MDF Multiplexed Master-Slave D-Type FlipFlop MDFRS Multiplexed Master-Slave D-Type FlipFlop with Set and Reset M3DF 3 to 1 Multiplexed Master-Slave D-Type Flip-Flop M3DFRS 3 to 1 Multiplexed Master-Slave D-Type Flip-Flop with Set and Reset JK J K Flip-Flop JKRS J K Flip-FLop with Set and Reset JBARK J K Flip-Flop JBARKRS J K Flip-Flop with Set and Reset BDL Buffered Data Latch BDLRS Buffered Data Latch with Set and Reset BDLARS Buffered Data Latch with Set and Reset BDF Buffered Master-Slave D-Type Flip-Flop BDFRS Buffered Master-Slave D-Type Flip-Flop with Set and Reset BMDF Buffered Multiplexed Master-Slave DType Flip-Flop BMDFRS Buffered Multiplexed Master-Slave DType Flip-Flop with Set and Reset TRID Tri-State Driver Intermediate Buffers: IBST1 IBST2 IBSK1 IBSK2 IBSK3 IBTRID Input Buffer with CMOS switching level Input Buffer with 2V switching level Driver with Lightly Skewed Outputs Driver with Medium Skewed Outputs Driver with Heavily Skewed Outputs Tri-State Driver
Input Buffer: IPNR IPR1P IPR1M IPR2P IPR2M IPR3P IPR3M IPR4P IPR4M Input Cell resistors) Input Cell Input Cell Resistor Input Cell Input Cell Resistor Input Cell Input Cell Resistor Input Cell Resistor Input Cell Resistor (with no Pullup or Pulldown with 1K-Ohm Pull-up Resistor with 1K-Ohm Pull-down with 2K-Ohm Pull-up Resistor with 2K-Ohm Pull-down with 4K-Ohm Pull-up Resistor with 4K-Ohm Pull-down with 100K-Ohm Pull-up with 100K-Ohm Pull-down
Output Buffers: OP1 OP2 OP3 OP6 OP12 OP5B OP11B OPT1 OPT2 OPT3 OPT6 Smallest Drive Output Buffer Small Drive Output Buffer Standard Drive Output Buffer Medium Drive Output Buffer Large Drive Output Buffer Standard Drive Non-Inverting Output Buffer Large Drive Non-Inverting Output Buffer Smallest Drive Tri-State Output Buffer Small Drive Tri-State Output Buffer Standard Drive Tri-State Output Buffer Medium Drive Tri-State Output Buffer
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CLA60000 Series
OPT12 OPT4B Large Drive Tri-State Output Buffer Standard Drive Non-Inverting Tri-State Output Buffer OPT10B Large Drive Non-Inverting Tri-State Output Buffer OPOD1 Smallest Drive Open-Drain Output Buffer OPOD2 Small Drive Open-Drain Output Buffer OPOD3 Standard Drive Open-Drain Output Buffer OPOD6 Medium Drive Open-Drain Output Buffer OPOD12 Large Drive Open-Drain Output Buffer OPOD5B Standard Drive Non-Inverting Open Drain Output Buffer OPOD11B Large Drive Non-Inverting Open Drain Output Buffer OPOS1 OPOS2 OPOS3 OPOS6 OPOS12 OPOS5B Smallest Drive Open-Source Output Buffer Small Drive Open-Source Output Buffer Standard Drive Open-Source Output Buffer Medium Drive Open-Source Output Buffer Large Drive Open-Source Output Buffer LAVP2 LAVP3 LAVP4 LAVP5 LAVM1 LAVM2 LAVM3 LAVM4 LAVM5 LAGND LAVDD Power Power Power Power Power Power Power Power Power Pad Pad Pad Pad Pad Pad Pad Pad Pad for for for for for for for for for Logic Logic Logic Logic Logic Logic Logic Logic Logic Array Array Array Array Array Array Array Array Array
Power Pad for Logic Array Power Pad for Logic Array
Analogue Cells: OSC1 Crystal Oscillator Peripheral Cell
ANIPCMP1 Comparator - Standard ANIPCMP2 Comparator - Low Power ANADC4 Four Bit Analogue To Digital Converter ANDAC4 Four Bit Digital To Analogue Converter ANVREFGN Reference Generator/Power On Reset ANVREFSH Shunt Regulator/Power On Reset a) Memory Cells
Standard Drive Non-Inverting OpenSource Output Buffer OPOS11B Large Drive Non-Inverting Open-Source Output Buffer Supply Pads: OPVP OPVM OPVPB OPVMB OPVPBB OPVMBB VDD Power Pad (Outputs) GND Power Pad (Outputs) VDD Power Pad (Outputs):Break in VDD GND Power Pad (Outputs):Break in GND VDD Power Pad (Outputs):Break in VDD and GND GND Power Pad (Outputs):Break in GND and VDD VDD Power Pad (Buffers) GND Power Pad (Buffers) VDD Power Pad (Buffers):Break in VDD GND Power Pad (Buffers):Break in GND VDD Power Pad (Buffers):Break in VDD and GND GND Power Pad (Buffers):Break in GND and VDD Power Pad for Logic Array
RAM2 RAM4 RAM8 RAM16 RAM32 RAM64
2 bit memory 4 bit memory 8 bit memory 16 bit memory 32 bit memory 64 bit memory
b) Single port decoder cells RAD2S RAD2SL RAD4S RAD4SL RAD8S RAD8SL RAD16S RAD16SL RAD32S RAD32SL RAD64S RAD64SL 2 words (1-16 bits RAM) 2 words (17-64 bits RAM) 4 words (1-16 bits RAM) 4 words (17-64 bits RAM) 8 words (1-16 bits RAM) 8 words (17-64 bits RAM) 16 words (1-16 bits RAM) 16 words (17-64 bits RAM) 32 words (1-16 bits RAM) 32 words (17-64 bits RAM) 64 words (1-16 bits RAM) 64 words (17-64 bits RAM)
IBVP IBVM IBVPB IBVMB IBVPBB IBVMBB
LAVP1
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CLA60000 Series
c) Dual port decoder cells
RAD2D RAD2DL RAD4D RAD4DL RAD8D RAD8DL RAD16D RAD16DL RAD32D RAD32DL RAD64D RAD64DL 2 words (1-16 bits RAM) 2 words (17-64 bits RAM) 4 words (1-16 bits RAM) 4 words (17-64 bits RAM) 8 words (1-16 bits RAM) 8 words (17-64 bits RAM) 16 words (1-16 bits RAM) 16 words (17-64 bits RAM) 32 words (1-16 bits RAM) 32 words (17-64 bits RAM) 64 words (1-16 bits RAM) 64 words (17-64 bits RAM) DRH4T10 DRI10 DRJ7 DRK7 4 line to 10 line Excess Gray to decimal decoder BCD to decimnal decoder/driver BCD to 7-Segment decoder/driver BCD to 7-Segment decoder/driver
d) Encoders ENA8T3 ENB10T4 8 line to 3 line priority encoder 10 line to 4 line priority encoder
e) Flip-Flops FFA8 FFB6 FFC4 FFD8 8 bit bistable latches 6 bit D-type flip-flops with clear 4 bit D-type flip-flops with clear and complementary outputs Octal D-type flip-flops with clear
Macro Cells: a) Adders ADA4 ADG4 4 bit binary full adders with fast carry Look ahead carry generator
f) ALU/Function generator FGA4 Arithmetic logic unit/function generator g) Magnitude comparator MCA4 4 bit magnitude comparators
b) Counters CNA4 CNB4 CNC4 CND4 CND4A CNE4 CNF4 CNG4 BCD counter/4 bit latch BCD decoder/ driver 4 bit counter latch 4 bit synchronous counter 4 bit synchronous binary up/down counter 4 bit synchronous binary up/down counter with reset 4 bit decade counter 4 bit synchronous binary counter 4 bit synchronous binary counter with enable
h) Multipliers MLA10 MLB4X4 MLW7 Decade rate multiplier 4 bit binary multiplier with tristate outputs 7 bit slice Wallace tree with tristate outputs
i) Multiplexors 8 line to 1 line data selector/multiplexer 4 line to 1 line data selector/multiplexer with tristate outputs MXB4T1A 4 line to 1 line data selector/multiplexer with inverted tristate outputs MXC2T1 Quad 2 line to 1 line data selector/ multiplexer MXC2T1A Quad 2 line to 1 line data selector/ multiplexer with inverted outputs MXD4T1 4 line to 1 line data selector/multiplexer MXE4T1 Dual 4 line to 1 line data selector/ multiplexer MXF2T1 Quad 2 line to 1 line multiplexer with storage MXA8T1 MXB4T1
c) Decoders DRA3T8 3 line to 8 line decoder/demultiplexer DRA4T16 4 line to 16 line decoder/demultiplexer DRA4T16A 4 line to 16 line decoder/demultiplexer with no enable DRB3T8 3 line to 8 line decoder/demultiplexer with address registers DRC3T8 3 line to 8 line decoder/demultiplexer with address latches DRD2T4 2 line to 4 line decoder/demultiplexer DRF4T101 4 line to 10 line BCD decoder DRG4T10 4 line to 10 line Excess 3 to decimal decoder
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CLA60000 Series
j) Parity generators PGA 9 bit odd/even generator/check SRD4 SRE4 SRE4 SRF8 SRG4 SRJ4 SRK5 i) Monitor PERF Performance monitor for CLA60000 4 bit parallel in serial out shift registers 4 bit parallel in serial out shift registers 4 bit parallel in serial out shift registers with J.KBAR input 8 bit shift and store register with tristate outputs 4 bit bidirectional universal shift registers 4 bit parallel access shift registers 5 bit shift register
k) Shift registers SRA2 SRA4 SRA8 SRA8A SRB2 SRB4 SRB8 SRB8A SRC8 2 bit parallel out serial shift registers with clear 4 bit parallel out serial shift registers with clear 8 bit parallel out serial shift registers with clear 8 bit parallel out serial shift registers with no clear 2 bit parallel in serial shift registers with clear 4 bit parallel in serial shift registers with clear 8 bit parallel in serial out shift registers with clear 8 bit parallel in serial out shift registers with no clear 8 bit parallel in serial out shift registers
m) Built in Test RGBIT RGCTL RGDIAG RGHOLD RGTBIT User Bit for use in BIST circuit Control unit for use in BIST circuits Diagnostic unit for use in BIST circuits Hold Bit for use in BIST circuit Test Bit for use in BIST circuit
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